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june 2014 docid026441 rev 1 1/43 AN4505 application note l3gd20: 3-axis digital output gyroscope introduction this document is intended to provide usage information and application hints related to st?s l3gd20 3-axial digital gyroscope. the l3gd20 is a three-axis angular rate sensor with a digital i 2 c/spi serial interface standard output. the device has a full scale of 250/500/ 2000 dps and is capable of measuring rates with a user-selectable bandwidth. the device may be configured to generate interrupt signals by an independent wake-up event. thresholds and timing of the interrupt generator are programmable by the end user on the fly. the l3gd20 has an integrated 32-level first-in first-out (fifo) buffer allowing the user to store data in order to limit intervention by the host processor. the l3gd20 is available in a small thin plastic land grid array package (lga 4x4x1) and it is guaranteed to operate over an extended temperature range from -40 c to +85 c. the ultra-small size and weight of the smd package make it an ideal choice for handheld portable applications such as cell phones and pdas, or any other application where reduced package size and weight are required. www.st.com
contents AN4505 2/43 docid026441 rev 1 contents 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 delay to switch modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 reading angular rate data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 startup sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 using the status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 using the data-ready (drdy) signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 using the block data update (bdu) feature . . . . . . . . . . . . . . . . . . . . . . . 11 3.5 level-sensitive/edge-sensitive data enable (den) . . . . . . . . . . . . . . . . . . 12 3.5.1 level-sensitive trigger stamping (lvlen = 1; extren = 0) . . . . . . . . . . 12 3.5.2 edge-sensitive trigger (lvlen = 0; extren = 1) . . . . . . . . . . . . . . . . . . 13 3.6 understanding angular rate data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6.1 data alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6.2 big-little endian selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6.3 example of angular rate data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 filter configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 low-pass filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 high-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.2 reference mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.3 autoreset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 interrupt pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2 interrupt configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
docid026441 rev 1 3/43 AN4505 contents 43 5.4 duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.5 selective axis movement and wake-up interrupts . . . . . . . . . . . . . . . . . . 24 5.5.1 wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.5.2 hp filter bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.5.3 using the hp filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.6 selective axis movement detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6 first-in first-out (fifo) buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1 fifo description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2 fifo registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2.1 control register 5 (0x24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2.2 fifo control register (0x2e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2.3 fifo source register (0x2f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3 fifo modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.3.1 bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.3.2 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.3.3 stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.3.4 stream-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.3.5 bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.4 watermark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.5 retrieving data from fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.1 example of delta temperature data calculation . . . . . . . . . . . . . . . . . . . . 41 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
list of tables AN4505 4/43 docid026441 rev 1 list of tables table 1. registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. operating mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. data rate configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. turn-on time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. den configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. output data registers content vs. angular rate (fs = 250 dps). . . . . . . . . . . . . . . . . . . . . . 14 table 8. ctrl_reg5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9. out_sel configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 10. int1_sel configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 11. low-pass filters cutoff frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 12. ctrl_reg2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 13. high-pass filter cutoff frequency [hz] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 14. high-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 15. reference mode lsb value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 16. ctrl_reg3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 17. ctrl_reg3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 18. int1_cfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 19. int1_cfg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 20. interrupt mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 21. int1_ths_xh register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 22. int1_ths_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 23. threshold lsb value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 24. int1_duration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 25. int1_duration description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 26. duration lsb value in normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 27. fifo buffer full representation (32nd sample set stored) . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 28. fifo overrun representation (33rd sample set stored and 1st sample discarded). . . . . . . 30 table 29. fifo enable bit in ctrl_reg5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 table 30. fifo_ctrl_reg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 31. fifo_src_reg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 32. fifo_src_reg behavior assuming wtm[4:0] = 15 (hex) . . . . . . . . . . . . . . . . . . . . . . . . 32 table 33. ctrl_reg3 (0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 34. out_temp register content. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 35. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
docid026441 rev 1 5/43 AN4505 list of figures 43 list of figures figure 1. data ready signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. data synchronization: level sensitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 3. level-sensitive trigger stamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4. data synchronization: edge sensitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 figure 5. low-pass/high-pass filter connections block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6. high-pass filter reset by reading the reference register . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7. reference mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8. autoreset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9. interrupt signals and interrupt pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. wait disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 11. wait enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12. no-move, wake-up interrupt generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 13. nm_wu_cfg high and low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 14. wake-up interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 15. no-move interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 16. fifo_en connections block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 17. fifo mode behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 18. stream mode fast reading behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 19. stream mode slow reading behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 20. stream mode slow reading zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 figure 21. stream-to-fifo mode: interrupt not latched . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 22. stream-to-fifo mode: interrupt latched . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 23. bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 24. watermark behavior - wtm[4:0] = 10 (hex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 25. fifo reading diagram - wtm[4:0] = 10 (hex). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
AN4505 registers docid026441 rev 1 6/43 1 registers table 1. registers register name address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 who_am_i 0fh 1 1 0 1 0 0 1 1 ctrl_reg1 20h dr1 dr0 bw1 bw0 pd zen yen xen ctrl_reg2 21h 0 0 hpm1 hpm0 hpcf3 hpcf2 hpcf1 hpcf0 ctrl_reg3 22h i1_int1 i1_boot h_lactive pp_od i2_drdy i2_wtm i2_orun i2_empty ctrl_reg4 23h bdu ble fs1 fs0 - - - sim ctrl_reg5 24h boot fifo_en -- hpen int1_sel1 int1_sel0 out_sel1 out_sel0 reference 25h ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 out_temp 26h temp7 temp6 temp5 temp4 temp3 temp2 temp1 temp0 status_reg 27h zyxor zor yor xor zyxda zda yda xda out_x_l 28h xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 out_x_h 29h xd15 xd14 xd13 xd12 xd11 xd10 xd9 xd8 out_y_l 2ah yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0 out_y_h 2bh yd15 yd14 yd13 yd12 yd11 yd10 yd9 yd8 out_z_l 2ch zd7 zd6 zd5 zd4 zd3 zd2 zd1 zd0 out_z_h 2dh zd15 zd14 zd13 zd12 zd11 zd10 zd9 zd8 fifo_ctrl_reg 2eh fm2 fm1 fm0 wtm4 wtm3 wtm2 wtm1 wtm0 fifo_src_reg 2fh wtm ovrn empty fss4 fss3 fss2 fss1 fss0 int1_cfg 30h and/or lir zhie zlie yhie ylie xhie xlie int1_src 31h - ia zh zl yh yl xh xl int1_ths_xh 32h - thsx14 thsx13 thsx12 thsx11 thsx10 thsx9 thsx8 int1_ths_xl 33h thsx7 thsx6 thsx5 thsx4 thsx3 thsx2 thsx1 thsx0 int1_ths_yh 34h - thsy14 thsy13 thsy12 thsy11 thsy10 thsy9 thsy8
AN4505 registers docid026441 rev 1 7/43 int1_ths_yl 35h thsy7 thsy6 thsy5 thsy4 thsy3 thsy2 thsy1 thsy0 int1_ths_zh 36h - thsz14 thsz13 thsz12 thsz11 thsz10 thsz9 thsz8 int1_ths_zl 37h thsz7 thsz6 thsz5 thsz4 thsz3 thsz2 thsz1 thsz0 int1_duration 38h wait d6 d5 d4 d3 d2 d1 d0 table 1. registers (continued) register name address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
operating modes AN4505 8/43 docid026441 rev 1 2 operating modes the l3gd20 provides three different operating modes, respectively cited as power-down mode, sleep mode and normal mode. after power supply is applied, the l3gd20 performs a 10 ms boot procedure to load the trimming parameter. after the boot is completed, the device is automatically configured in power-down mode. referring to the l3gd20 datasheet, output data rate (odr), power down (pd) and zen, yen, xen bits of ctrl_reg1 are used to select the operating modes (power-down mode, sleep mode and normal mode) and output data rate ( table 2 and table 3 ). table 2. operating mode selection operating mode pd zen yen xen power-down 0 - - - sleep 1 0 0 0 normal 1 - - - table 3. data rate configuration dr [1:0] bw [1:0] odr [hz] cutoff lpf1 [hz] cutoff lpf2 [hz] 00 00 95 32 12.5 00 01 95 25 00 10 95 25 00 11 95 25 01 00 190 54 12.5 01 01 190 25 01 10 190 50 01 11 190 70 10 00 380 78 20 10 01 380 25 10 10 380 50 10 11 380 110 11 00 760 93 30 11 01 760 35 11 10 760 50 1 11 760 110
docid026441 rev 1 9/43 AN4505 operating modes 43 table 4 shows the typical values of power consumption for the different operating modes. power consumption in normal mode is independent of the selected odr. 2.1 power-down mode when the device is in power-down mode, almost all internal blocks of the device are switched off to minimize power consumption. digital interfaces (i 2 c and spi) are still active to allow communication with the device. the content of the configuration registers is preserved and output data registers are not updated, therefore keeping the last data sampled in memory before going into power-down mode. 2.2 sleep mode while the device is in sleep mode the driving circuitry making the moving mass of the gyroscope oscillating is kept active. turn-on time from sleep mode to normal mode is drastically reduced. 2.3 normal mode in normal mode, data are generated at the data rate (odr) selected through the dr bits. data interrupt generation is active and configured through the int1_cfg register. 2.4 delay to switch modes the delay in order to switch modes is shown in table 5 . table 4. power consumption operating mode power consumption power-down 5 a sleep 2 ma normal 6.1 ma table 5. turn-on time starting mode target mode turn-on time - typ power-down normal 250 ms power-down self test 250 ms sleep normal 1/odr: lpf2 disabled 6/odr: lpf2 enabled normal sleep immediate normal power-down immediate other settings change - 1/odr: lpf2 disabled 6/odr: lpf2 enabled
reading angular rate data AN4505 10/43 docid026441 rev 1 3 reading angular rate data 3.1 startup sequence once the device is powered-up, it automatically downloads the calibration coefficients from the embedded flash to the internal registers. when the boot procedure is completed, i.e. after approximately 10 milliseconds, the device automatically enters power-down mode. to turn on the device and gather angular rate data, it is necessary to select one of the operating modes through ctrl_reg1 and to enable at least one of the axes. the following general-purpose sequence can be used to configure the device: 3.2 using the status register the device is provided with a status_reg which should be polled to check when a new set of data is available. the reads should be performed as follows: 1. write ctrl_reg2 2. write ctrl_reg3 3. write ctrl_reg4 4. write ctrl_reg6 5. write reference 6. write int1_ths 7. write int1_dur 8. write int1_cfg 9. write ctrl_reg5 10. write ctrl_reg1 1. read status_reg 2. if status_reg(3) = 0, then go to 1 3. if status_reg(7) = 1, then some data have been overwritten 4. read out_x_l 5. read out_x_h 6. read out_y_l 7. read out_y_h 8. read out_z_l 9. read out_z_h 10. data processing 11. go to 1
docid026441 rev 1 11/43 AN4505 reading angular rate data 43 the check performed at step 3 allows understanding whether the reading rate is adequate compared to the data production rate. in case one or more angular rate samples have been overwritten by new data, because of an insufficient reading rate, the zyxor bit of status_reg is set to 1. the overrun bits are automatically cleared when all the data present inside the device have been read and new data have not been produced in the meantime. 3.3 using the data-ready (drdy) signal the device may be configured to have one hw signal to determine when a new set of measurement data is available for reading. this signal is represented by the zyxda bit of status_reg. the signal can be driven to the drdy/int2 pin by setting the i2_drdy bit of ctrl_reg3 to 1 and its polarity set to active-low or active-high through the h_lactive bit of ctrl_reg3 (see section 5.1 ). the data-ready signal rises to 1 when a new set of angular rate data has been generated and it is available for reading.the interrupt is reset when the higher part of one of the enabled channels has been read (29h, 2bh, 2dh). figure 1. data ready signal 3.4 using the block data update (bdu) feature if reading the angular rate data is particularly slow and cannot be synchronized (or it is not required) with either the zyxda bit present inside the status_reg or with the drdy signal, it is strongly recommended to set the bdu (block data update) bit in ctrl_reg4 to 1. this feature avoids reading values (most significant and least significant parts of the angular rate data) related to different samples. in particular, when the bdu is activated, the data registers related to each channel always contain the most recent angular rate data produced by the device, but, in case the reading of a given pair (i.e. out_x_h and out_x_l, out_y_h and out_y_l, out_z_h and out_z_l) is initiated, the refresh for that pair is blocked until both msb and lsb parts of the data are read. note: bdu only guarantees that out_x(y, z)_l and out_x(y,z)_h have been sampled at the same moment. for example, if the reading speed is too slow, it may read x and y sampled at t1 and z sampled at t2. ".w '5'< '$7$5($' 1 h o s p d 6 1 h o s p d 6 $1*8/$5 5$7( '$7$ ;<= ;<=
reading angular rate data AN4505 12/43 docid026441 rev 1 3.5 level-sensitive/edge-sensitive data enable (den) the l3gd20 allows external trigger level recognition by enabling the extren (bit 7) and lvlen (bit 6) bits in reserved (11h). two different modes can be used: level-sensitive or edge-sensitive trigger. the den input signal is driven on pin 8 (reserved). 3.5.1 level-sensitive trigger stamping (lvlen = 1; extren = 0) once enabled, the den logical value replaces the less significant bit of x, y and z data for the axis selected through the xen, yen, zen bits in ctrl_reg1 (20h) until the den logical value is kept high. data are stored inside the fifo with the internally selected odr. figure 2. data synchronization: level sensitive figure 3. level-sensitive trigger stamping table 6. den configurations extren lvlen function 0 1 level sensitive 1 0 edge sensitive
docid026441 rev 1 13/43 AN4505 reading angular rate data 43 3.5.2 edge-sensitive trigger (lvlen = 0; extren = 1) once enabled, fifo and output data are updated only with the first sample of x, y and z data generated after every rising edge of the den input signal. the den signal must be high while a new data sample is generated in order to update data in fifo and output registers. when the odr selected is 800 hz, the maximum den sample frequency is f den = 1/t den = 400 hz (downsampling is useful). figure 4. data synchronization: edge sensitive
reading angular rate data AN4505 14/43 docid026441 rev 1 3.6 understanding angular rate data the measured angular rate data are sent to the out_x_h, out_x_l, out_y_h, out_y_l, out_z_h, and out_z_l registers. these registers contain, respectively, the most significant part and the least significant part of the angular rate signals acting on the x, y, and z axes. the complete angular rate data for the x (y, z) channel is given by the concatenation out_x_h & out_x_l (out_y_h & out_y_l, out_z_h & out_z_l) and it is expressed as a two?s complement number. 3.6.1 data alignment angular rate data are represented as 16-bit numbers and are left-justified. 3.6.2 big-little endian selection the l3gd20 allows swapping the content of the lower and the upper part of the angular rate registers (i.e. out_x_h with out_x_l), in order to be compliant with both little-endian and big-endian data representations. ?little endian? means that the low-order byte of the number is stored in memory at the lowest address, and the high-order byte at the highest address. (the little end comes first). this mode corresponds to bit ble in ctrl_reg4 set to 0 (default configuration). on the contrary, ?big endian? means that the high-order byte of the number is stored in memory at the lowest address, and the low-order byte at the highest address. 3.6.3 example of angular rate data table 7 provides a few basic examples of the data that is read in the data registers when the device is subject to a given angular rate. the values listed in the table are given under the hypothesis of perfect device calibration (i.e. no offset, no gain error,....) and practically show the effect of the ble bit. table 7. output data registers content vs. angular rate (fs = 250 dps) angular rate values ble = 0 ble = 1 register address 28h 29h 28h 29h 0 dps 00h 00h 00h 00h 100 dps a4h 2ch 2ch a4h 200 dps 49h 59h 59h 49h -100 dps 5ch c4h c3h 5ch -200 dps b7h a6h a6h b7h
docid026441 rev 1 15/43 AN4505 digital filters 43 4 digital filters the l3gd20 provides embedded low-pass and as well as high-pass filtering capability to easily delete the dc component of the measured angular rate. as shown in figure 5 , through hpen, int1_sel[1:0] and out_sel[1:0] bits of ctrl_reg5 configuration, it is possible to independently apply the filter on the output/fifo data and/or on the interrupts data. this means that it is possible, i.e., to get filtered data while interrupt generation works on unfiltered data. figure 5. low-pass/high-pass filter connections block diagram 4.1 filter configurations referring to table 9 , the hpen and out_sel[1:0] bits are used to drive unfiltered or filtered data to the output registers and to the fifo: table 8. ctrl_reg5 register boot fifo_en - hpen int1_sel1 int1_sel0 out_sel1 out_sel0 $0y $'& /3) +3) +3hq /3) 2xwb6ho! 'dwd5hj ),)2 [[ ,qwhuuxsw jhqhudwru ,17b6ho! table 9. out_sel configuration setting hpen out_sel1 out_sel0 description x00 data in datareg and fifo are not high-pass filtered x01 data in datareg and fifo are high-pass filtered 01x data in datareg and fifo are low-pass filtered by lpf2 11x data in datareg and fifo are high-pass and low-pass filtered by lpf2
digital filters AN4505 16/43 docid026441 rev 1 referring to table 10 , hpen and int1_sel[1:0] bits are used to drive unfiltered or filtered data to the interrupt generator circuitry. 4.2 low-pass filters the bandwidth of the low-pass filters depends on the selected odr. the cutoff frequencies (f t ) of the low-pass filters are shown in table 11 . table 10. int1_sel configuration setting hpen in1t_sel1 int1_sel0 description x00 non high-pass filtered data are used for the interrupt generator x01 high-pass filtered data are used for the interrupt generator 01x low-pass filtered data are used for the interrupt generator 11x high-pass and low-pass filtered data are used for the interrupt generator table 11. low-pass filters cutoff frequency dr [1:0] bw [1:0] odr [hz] cutoff lpf1 [hz] cutoff lpf2 [hz] 00 00 95 32 12.5 00 01 95 25 00 10 95 25 00 11 95 25 01 00 190 54 12.5 01 01 190 25 01 10 190 50 01 11 190 70 10 00 380 78 20 10 01 380 25 10 10 380 50 10 11 380 110 11 00 760 93 30 11 01 760 35 11 10 760 50 1 11 760 110
docid026441 rev 1 17/43 AN4505 digital filters 43 4.3 high-pass filter the bandwidth of the high-pass filter depends on the selected odr and on the settings of hpcfx bits of ctrl_reg2. the high-pass filter cutoff frequencies (f t ) are shown in table 13 . referring to table 14 , three operating modes are possible for the high-pass filter. table 12. ctrl_reg2 register 0 (1) 1. value loaded at boot. this value must not be changed 0 (1) hpm1 hpm0 hpcf3 hpcf2 hpcf1 hpcf0 table 13. high-pass filter cutoff frequency [hz] hpcf[3:0] odr [hz] 95 190 380 760 0000 8 15 30 56 0001 4 8 15 30 0010 2 4 8 15 0011 1 2 4 8 0100 0.5 1 2 4 0101 0.2 0.5 1 2 0110 0.1 0.2 0.5 1 0111 0.05 0.1 0.2 0.5 1000 0.02 0.05 0.1 0.2 1001 0.01 0.02 0.05 0.1 table 14. high-pass filter mode configuration hpm1 hpm0 high-pass filter mode 0 0 normal mode (reset by reading the reference register) 0 1 reference signal for filtering 1 0 normal mode (reset by reading the reference register) 1 1 autoreset on interrupt event
digital filters AN4505 18/43 docid026441 rev 1 4.3.1 normal mode in this configuration the high-pass filter can be reset by reading the reference register, instantly deleting the dc component of the angular rate. figure 6. high-pass filter reset by reading the reference register 4.3.2 reference mode in this configuration the output data is calculated as the difference between the input angular rate and the content of the reference register. this register is in two?s complement representation and the value of 1 lsb of these 8-bit registers depends on the selected full scale ( table 15 ). ".w ,qsxw$ffhohudwlrq )lowhuhg'dwd table 15. reference mode lsb value full scale reference mode lsb value (mdps) 250 ~2 500 ~4 2000 ~16
docid026441 rev 1 19/43 AN4505 digital filters 43 figure 7. reference mode 4.3.3 autoreset in this configuration the filter is automatically reset when the configured interrupt event occurs. reference is, however, used to set the filter instantaneously. note: the xyz dataset used to reset the filter is the one after the interrupt. figure 8. autoreset ".w ,qsxw$ffhohudwlrq )lowhuhg'dwd 5()(5(1&(hqdeoh 5()(5(1&( am08454v1 filtered data reference enable input acceleration
interrupt generation AN4505 20/43 docid026441 rev 1 5 interrupt generation the l3gd20 interrupt signal can be configured in a very flexible way allowing to recognize independent rotations of the x-,y- and z-axis. the interrupt signal can be driven to the int1 pin. the int2 pin is dedicated to drdy and fifo interrupts. 5.1 interrupt pin configuration the device is provided with two pins which can be activated to generate either the data- ready or the interrupt signals. the functionality of the pins is selected through ctrl_reg3(22h). refer to table 17 and to the block diagram given in figure 9 . figure 9. interrupt signals and interrupt pins table 16. ctrl_reg3 register i1_int1 i1_boot h_lactive pp_od i2_drdy i2_wtm i2_orun i2_empty table 17. ctrl_reg3 description i1_int1 interrupt enable on the int1 pin. default value 0. (0: disable; 1: enable) i1_boot boot status available on int1. default value 0. (0: disable; 1: enable) h_lactive interrupt active configuration on int1. default value 0. (0: high; 1:low) pp_od push-pull / open drain. default value: 0. (0: push-pull; 1: open drain) i2_drdy date ready on drdy/int2. default value 0. (0: disable; 1: enable) i2_wtm fifo watermark interrupt on drdy/int2. default value: 0. (0: disable; 1: enable) i2_orun fifo overrun interrupt on drdy/int2 default value: 0. (0: disable; 1: enable) i2_empty fifo empty interrupt on drdy/int2. default value: 0. (0: disable; 1: enable) $0y ,17b&)* $1'25 &75/b5(* ,b%rrw &75/b5(* ,b'5'< &75/b5(* ,b:70 &75/b5(* ,b25xq &75/b5(* ,b(psw\ ,17sdg &75/b5(* ,17sdg
docid026441 rev 1 21/43 AN4505 interrupt generation 43 5.2 interrupt configuration the l3gd20 offers several possibilities to personalize the interrupt signal. the registers involved in the interrupt generation behavior are int1_cfg, int1_ths and int1_duration. whenever an interrupt condition is verified the interrupt signal is generated and by reading the int1_src register it is possible to understand which condition happened. reading int1_src also clears the int1_src ia bit (and eventually the interrupt signal on the int1 pin) and allows the refresh of data in the int1_src register if the latched option was chosen. table 18. int1_cfg register and/or lir zhie zlie yhie ylie xhie xlie table 19. int1_cfg description and/or and/or combination of interrupt events. default value: 0 (0: or combination of interrupt events 1: and combination of interrupt events lir latch interrupt request. default value: 0 (0: interrupt request not latched; 1: interrupt request latched) cleared by reading int1_src reg. zhie enable interrupt generation on z high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured rate value higher than preset threshold) zlie enable interrupt generation on z low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured rate value lower than preset threshold) yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured rate value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured rate value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured rate value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured rate value lower than preset threshold) table 20. interrupt mode configuration and/or interrupt mode 0 or combination of interrupt events 1 and combination of interrupt events
interrupt generation AN4505 22/43 docid026441 rev 1 5.3 threshold threshold registers int1_ths_xh and int_ths_xl (respectively msb and lsb) define the reference angular rates used by the interrupt generation circuitry. the value of 1 lsb of the threshold depends on the selected full scale ( table 23 ). 5.4 duration the content of the dx bits of the duration register sets the minimum duration of the interrupt event to be recognized. the duration steps and maximum values depend on the odr chosen. the duration time is measured in n/odr, where n is the content of the duration register and the odr is 100, 200, 400, 800. table 21. int1_ths_xh register - thsx14 thsx13 thsx12 thsx11 thsx10 thsx9 thsx8 table 22. int1_ths_xl register thsx7 thsx6 thsx5 thsx4 thsx3 thsx2 thsx1 thsx0 table 23. threshold lsb value full scale [dps] threshold lsb value (mdps) 250 ~7.6 500 ~15.2 2000 ~61 table 24. int1_duration register wait d6 d5 d4 d3 d2 d1 d0 table 25. int1_duration description wait wait enable. default value: 0 (0: disable; 1: enable) d6 - d0 duration value. default value: 000 0000 table 26. duration lsb value in normal mode odr (hz) duration lsb value (ms) 95 10.5 190 5.26 380 2.63 760 1.32
docid026441 rev 1 23/43 AN4505 interrupt generation 43 the wait bit of the int1_duration register has the following meaning: wait = ?0?: the interrupt falls immediately if the signal crosses the selected threshold ( figure 10 ) wait = ?1?: if the signal crosses the selected threshold, the interrupt falls only after the duration has counted the number of samples at the selected data rate, written into the duration counter register ( figure 11 ). figure 10. wait disabled figure 11. wait enabled ? wait bit = ?0? interrupt disabled as soon as condition is no longer valid (ex: ra te value below threshold) rate (dps) rate threshold 0 t(n) t(n) t(n) interrupt counter duration value ?wait? disabled ? wait bit = ?1? interrupt disabled after duration sample (sort of hysteresis) rate (dps) rate threshold 0 t(n) t(n) t(n) interrupt counter duration value ?wait? enabled duration value is the same used to validate interrupt
interrupt generation AN4505 24/43 docid026441 rev 1 5.5 selective axis movement and wake-up interrupts the l3gd20 interrupts signal can behave as selective axis movement detection and wake- up. whenever an interrupt condition is verified, the interrupt signal is generated and by reading the int1_src register it is possible to understand which condition happened. the selective axis movement detection signal (sa) and wake-up signal (wu) interrupt generation block is represented in figure 12 . the sa or wu interrupt generation is selected through the and/or bit in the int1_cfg register. if the and/or bit is ?0?, signals coming from comparators for the axis enabled through the int1_cfg register are put in logical or. in this case, interrupt is generated when at least one of the enabled axes exceeds the threshold written in the module in the int1_ths_xh and int1_ths_xl registers. otherwise, if the and/or bit is ?1?, signals coming from comparators enter a ?nand? port. in this case an interrupt signal is generated only if all the enabled axes are passing the threshold. the lir bit of int1_cfg allows deciding if the interrupt request must be latched or not. if the lir bit is ?0? (default value), the interrupt signal goes high when the interrupt condition is satisfied and returns to low immediately if the interrupt condition is no longer verified. otherwise, if the lir bit is ?1?, whenever an interrupt condition is applied the interrupt signal remains high even if the condition returns to a non-interrupt status until a read of the int1_src register is performed. the zhie, zlie, yhie, ylie, xhie, and xlie bits of the int1_cfg register allow deciding on which axis the interrupt decision must be performed and on which direction the threshold must be passed to generate the interrupt request. figure 12. no-move, wake-up interrupt generator $0y 7+6uhj _e_!d" _e_d" 5d w h b ; ;+,( ;/,( 6$ )) ,17b&)* _e_!d" _e_d" <+,( </,( _e_!d" _e_d" =+,( =/,( 5d w h b < 5d w h b = ,17b&)* d e d e
docid026441 rev 1 25/43 AN4505 interrupt generation 43 the threshold module which is used by the system to detect any no-move or wake-up event is defined by the int1_ths register. the threshold value is expressed over 7 bits as an unsigned number and is symmetrical around the zero-g level. xh (yh, zh) is true when the unsigned angular rate value of the x (y, z) channel is higher than int1_ths. similarly, xl (yl, zl) low is true when the unsigned angular rate value of the x (y, z) channel is lower than int1_ths. refer to figure 13 for more details. figure 13. nm_wu_cfg high and low 5.5.1 wake-up wake-up interrupt refers to a specific configuration of the int1_cfg register that allows interrupt generation when the angular rate on the configured axis exceeds a defined threshold ( figure 14 ). figure 14. wake-up interrupt $0y )xoo6fdoh )xoo6fdoh gsvohyho 7kuhvkrogprgxoh 7kuhvkrogprgxoh ;<=kljk ;<=kljk ;<=orz 3rvlwlyh 1hjdwlyh udwh udwh :$.(83 7+ 5 (6 +2/' :.3,qwhuuxsw gsv :$.(83 7+ 5 (6 +2/' :.3,qwhuuxsw
interrupt generation AN4505 26/43 docid026441 rev 1 5.5.2 hp filter bypassed this paragraph provides a basic algorithm which shows the practical use of the wake-up feature. in particular, with the code below, the device is configured to recognize when the absolute angular rate along either the x-, y-, or z-axis exceeds a preset threshold (100 dps used in the example). the event which triggers the interrupt is latched inside the device and its occurrence is signaled through the use of the int1 pin. 5.5.3 using the hp filter the code provided below gives a basic routine which shows the practical use of the wake- up feature performed on high-pass filtered data. in particular the device is configured to recognize when the high-frequency component of the angular rate applied along either the x-, y-, or z-axis exceeds a preset threshold (100 dps used in the example). the event which triggers the interrupt is latched inside the device and its occurrence is signaled through the use of the int1 pin. 1 write 0fh into ctrl_reg1 // turn-on the sensor and enable x, y, and z // odr = 100 hz 2 write 00h into ctrl_reg2 // high-pass filter disabled 3 write 80h into ctrl_reg3 // interrupt driven to int1 pad 4 write 00h into ctrl_reg4 // fs = 250 dps 5 write 2ch into int1_ths_xh // threshold = 100 dps 6 write a4h into int1_ths_xl // threshold = 100 dps 7 write 00h into int1_duration // duration = 0 8 write 02h into int1_cfg // enable xh interrupt generation 9 poll int1 pad; if int1=0 then go to 8 // poll int1 pin waiting for the // wake-up event 10 read int1_src // return the event that has triggered the // interrupt 11 (wake-up event has occurred; insert your code here) // event handling 12 go to 8 1 write 0fh into ctrl_reg1 // turn-on the sensor and enable x, y, and z // odr = 100 hz 2 write 00h into ctrl_reg2 // high-pass filter in normal mode 3 write 80h into ctrl_reg3 // interrupt driven to int1 pad 4 write 00h into ctrl_reg4 // fs = 250 dps 5 write 05h into ctrl_reg5 // data in datareg and fifo are high-pass filtered // high-pass filtered data are used for interrupt // generation 6 write 2ch into int1_ths_xh // threshold = 100 dps 7 write a4h into int1_ths_xl // threshold = 100 dps
docid026441 rev 1 27/43 AN4505 interrupt generation 43 at step 13, a dummy read of the reference register is performed to set the current/reference angular rate/tilt state against which the device performed the threshold comparison. this read may be performed any time it is required to set current rate as a reference state without waiting for the filter to settle. 5.6 selective axis movement detection selective axis movement detection refers to a specific configuration of the int1_cfg and int1_ths registers that allows recognizing when the device is rotating only around the selected axis. referring to figure 15 , a ?no rotation zone? is defined around the zero-dps level where the angular rates are small enough to be considered as zero. it is possible to create a configuration of int1_cfg register so that an interrupt is generated only if, i.e., angular rates for rotation around the x and y axes are around zero while it is different from zero for the z-axis. this means the device is doing a pure yaw rotation. 8 write 2ch into int1_ths_yh // threshold = 100 dps 9 write a4h into int1_ths_yl // threshold = 100 dps 10 write 2ch into int1_ths_zh // threshold = 100 dps 11 write a4h into int1_ths_zl // threshold = 100 dps 12 write 00h into int1_duration // duration = 0 13 read reference // dummy read to force the hp filter to // current angular rate value // (i.e. set reference angular rate) 14 write 6ah into int1_cfg // enable xh, yh and zh interrupt generation // interrupt latched 15 poll int1 pad; if int1=0 then go to 8 // poll int1 pin waiting for the // wake-up event 16 read int1_src // return the event that has triggered the // interrupt 17 (wake-up event has occurred; insert your code here) // event handling 18 go to 15
interrupt generation AN4505 28/43 docid026441 rev 1 figure 15. no-move interrupt this paragraph provides the basics for the use of the selective axis movement detection feature. the example code which implements the sw routine for the selective axis movement recognition is given below. the code sample exploits a threshold set at 60 dps selective axis movement detection and the event is notified by the hardware signal int1. at step 12, the int1_duration register is configured like this to ignore events that are shorter than 1/dr = 1/100 ~= 10 msec in order to avoid false detections. once the selective axis movement detection has occurred, a read of the int1_src register clears the request and the device is ready to recognize other events. 1 write 0fh into ctrl_reg1 // turn-on the sensor and enable x, y, and z // odr = 100 hz 3 write 80h into ctrl_reg3 // interrupt driven to int1 pad 4 write 00h into ctrl_reg4 // fs = 250 dps 6 write 2ch into int1_ths_xh // threshold = 60 dps 7 write a4h into int1_ths_xl // threshold = 60 dps 8 write 2ch into int1_ths_yh // threshold = 60 dps 9 write a4h into int1_ths_yl // threshold = 60 dps 10 write 2ch into int1_ths_zh // threshold = 60 dps 11 write a4h into int1_ths_zl // threshold = 60 dps 12 write 01h into int1_duration // duration = 10 ms 13 write 65h into int1_cfg // enable xl, yl and zh interrupt generation in and // configuration. interrupt latched 14 poll int1 pad; if int1=0 then go to 8 // poll int1 pin waiting for the // wake-up event 15 read int1_src // return the event that has triggered the // interrupt 16 (wake-up event has occurred; insert your code here) // event handling 17 go to 15 $0y gsv 12527$7,21 =21( ; < = 6hohfwlyh$[lv ,qwhuuxsw
docid026441 rev 1 29/43 AN4505 first-in first-out (fifo) buffer 43 6 first-in first-out (fifo) buffer in order to decrease the host processor interaction and facilitate post-processing data for event recognition, the l3gd20 embeds a first-in first-out buffer (fifo) for each of the three output channels, x, y, and z. fifo use allows consistent power saving for the system, it can wake-up only when needed and burst the significant data out from the fifo. the fifo buffer can work according to five different modes that guarantee a high-level of flexibility during application development: bypass mode, fifo mode, stream mode, stream-to-fifo mode and bypass-to-stream mode. the programmable watermark level and fifo overrun events can be enabled to generate dedicated interrupts on the drdy/int2 pin. 6.1 fifo description the fifo buffer is able to store up to 32 angular rate samples of 16 bits for each channel; data are stored in the 16-bit two?s complement left-justified representation. the data samples set consists of 6 bytes (xl, xh, yl, yh, zl, and zh) and they are released to the fifo at the selected output data rate (odr). the new sample set is placed in the first empty fifo slot until the buffer is full, therefore, the oldest value is overwritten. table 27. fifo buffer full representation (32 nd sample set stored) output registers 0x28h 0x29h 0x2ah 0x2bh 0x2ch 0x2dh xl(0) xh(0) yl(0) yh(0) zl(0) zh(0) fifo index fifo sample set fifo(0) xl(0) xh(0) yl(0) yh(0) zl(0) zh(0) fifo(1) xl(1) xh(1) yl(1) yh(1) zl(1) zh(1) fifo(2) xl(2) xh(2) yl(2) yh(2) zl(2) zh(2) fifo(3) xl(3) xh(3) yl(3) yh(3) zl(3) zh(3) ... ... ... ... ... ... ... ... ... ... ... ... ... ... fifo(30) xl(30) xh(30) yl(30) yh(30) zl(30) zh(30) fifo(31) xl(31) xh(31) yl(31) yh(31) zl(31) zh(31)
first-in first-out (fifo) buffer AN4505 30/43 docid026441 rev 1 table 27 represents the fifo full status when 32 samples are stored in the buffer while table 28 represents the next step when the 33 rd sample is inserted into fifo and the 1 st sample is overwritten. the new oldest sample set is made available in the output registers. when fifo is enabled and the mode is different from bypass, the l3gd20 output registers (28h to 2dh) always contain the oldest fifo sample set. 6.2 fifo registers the fifo buffer is managed by three different accelerometer registers, two of these allow enabling and configuring fifo behavior, the third provides information about the buffer status. 6.2.1 control register 5 (0x24) the fifo_en bit in ctrl_reg5 must be set to 1 in order to enable the internal first-in first- out buffer; when this bit is set, the gyroscope output registers (28h to 2dh) don?t contain the current angular rate value but they always contain the oldest value stored in fifo. table 28. fifo overrun representation (33 rd sample set stored and 1 st sample discarded) output registers 0x28h 0x29h 0x2ah 0x2bh 0x2ch 0x2dh xl(1) xh(1) yl(1) yh(1) zl(1) zh(1) fifo index sample set fifo(0) xl(1) xh(1) yl(1) yh(1) zl(1) zh(1) fifo(1) xl(2) xh(2) yl(2) yh(2) zl(2) zh(2) fifo(2) xl(3) xh(3) yl(3) yh(3) zl(3) zh(3) fifo(3) xl(4) xh(4) yl(4) yh(4) zl(4) zh(4) ... ... ... ... ... ... ... ... ... ... ... ... ... ... fifo(30) xl(31) xh(31) yl(31) yh(31) zl(31) zh(31) fifo(31) xl(32) xh(32) yl(32) yh(32) zl(32) zh(32) table 29. fifo enable bit in ctrl_reg5 b7 b6 b5 b4 b3 b2 b1 b0 x fifo_en x xxxxx
docid026441 rev 1 31/43 AN4505 first-in first-out (fifo) buffer 43 figure 16. fifo_en connections block diagram 6.2.2 fifo control register (0x2e) this register is dedicated to fifo mode selection and watermark configuration. fm[2:0] bits are dedicated to defining the fifo buffer behavior: 1. fm[2:0] = (0,0,0): bypass mode 2. fm[2:0] = (0,0,1): fifo mode 3. fm[2:0] = (0,1,0): stream mode 4. fm[2:0] = (0,1,1): stream-to-fifo mode 5. fm[2:0] = (1,0,0): bypass-to-stream mode the trigger used to activate stream-to-fifo and bypass-to-stream modes is related to the ia bit value of the selected int1_src register and does not depend on the interrupt pin value and polarity. the trigger is generated also if the selected interrupt is not driven to an interrupt pin. the wtm[4:0] bits are intended to define the watermark level; when fifo content exceeds this value, the wtm bit is set to ?1? in the fifo source register. $0y ),)2 %xiihu $'& 2xwsxw5hjlvwhuv &75/b5(*),)2b(1 0hdvxuhphqw &kdlq ),)2 %xiihu $'& 2xwsxw5hjlvwhuv &75/b5(*),)2b(1 table 30. fifo_ctrl_reg b7 b6 b5 b4 b3 b2 b1 b0 fm2 fm1 fm0 wtm4 wtm3 wtm2 wtm1 wtm0
first-in first-out (fifo) buffer AN4505 32/43 docid026441 rev 1 6.2.3 fifo source register (0x2f) this register is updated at every odr and provides information about the fifo buffer status. ? wtm bit is set high when fifo content exceeds watermark level. ? ovrn bit is set high when fifo buffer is full, this means that the fifo buffer contains 32 unread samples. at the following odr a new sample set replaces the oldest fifo value. the ovrn bit is reset when the first sample set has been read. ? empty flag is set high when all fifo samples have been read and fifo is empty. ? fss[4:0] field always contains the current number of unread samples stored in the fifo buffer. when fifo is enabled, this value increases at odr frequency until the buffer is full, whereas, it decreases every time that one sample set is retrieved from fifo. register content is updated synchronous to the fifo write and read operation. the watermark flag, the fifo overrun and fifo empty events can be enabled to generate a dedicated interrupt on the drdy/int2 pin by configuring ctrl_reg3. ? i2_wtm bit drives the watermark flag (wtm) on the drdy/int2 pin. ? i2_ovrn bit drives the overrun event (ovrn) on the drdy/int2y pin. ? i2_empty bit drives the empty event (empty) on the drdy/int2 pin if one ore more bits are set to ?1?, the drdy/int2 pin status is the logical or combination of the three signals. table 31. fifo_src_reg b7 b6 b5 b4 b3 b2 b1 b0 wtm ovrn empty fss4 fss3 fss2 fss1 fss0 table 32. fifo_src_reg behavior assuming wtm[4:0] = 15 (hex) wtm ovrn empty fss[4:0] unread fifo samples timing 0 0 1 00000 0 t0 0 0 0 00001 1 t0 + 1/odr 0 0 0 00010 2 t0 + 2/odr ... ... ... ... ... ... 0 0 0 01111 15 t0 + 15/odr 1 0 0 10000 16 t0 + 16/odr ... ... ... ... ... ... 1 0 0 11110 30 t0 + 30/odr 1 0 0 11111 31 t0 + 31/odr 1 1 0 11111 32 t0 + 32/odr table 33. ctrl_reg3 (0x22) b7 b6 b5 b4 b3 b2 b1 b0 x x x x x i2_wtm i2_orun i2_empty
docid026441 rev 1 33/43 AN4505 first-in first-out (fifo) buffer 43 6.3 fifo modes the l3gd20 fifo buffer can be configured to operate in five different modes selectable by the fm[2:0] field in fifo_ctrl_reg. available configurations ensure a high level of flexibility and extend the number of functions usable in application development. bypass, fifo, stream, stream-to-fifo and bypass-to-stream modes are described in the following paragraphs. 6.3.1 bypass mode when bypass mode is enabled, fifo is not operational: buffer content is cleared, output registers (0x28 to 0x2d) are frozen at the last value loaded, and the fifo buffer remains empty until another mode is selected. follow these steps for bypass mode configuration: 1. turn on fifo by setting the fifo_en bit to ?1? in control register 5 (0x24). after this operation the fifo buffer is enabled but isn?t collecting data, output registers are frozen to the last samples set loaded. 2. activate bypass mode by setting the fm[2:0] field to ?000? in the fifo control register (0x2e). if this mode is enabled, the fifo source register (0x2f) is forced equal to 0x20. bypass mode must be used in order to stop and reset the fifo buffer when a different mode is operating. note that placing the fifo buffer into bypass mode clears the whole buffer content. 6.3.2 fifo mode in fifo mode, the buffer continues filling until full (32 sample set stored) then it stops collecting data and the fifo content remains unchanged until a different mode is selected. follow these steps for fifo mode configuration: 1. turn on fifo by setting the fifo_en bit to ?1? in control register 5 (0x24). after this operation the fifo buffer is enabled but isn?t collecting data, output registers are frozen to the last samples set loaded. 2. activate fifo mode by setting the fm[2:0] field to ?001? in the fifo control register (0x2e). by selecting this mode, fifo starts data collection and source register (0x2f) changes according to the number of samples stored. at the end of the procedure, the source register is set to 0xdf and the ovrn flag generates an interrupt if the i2_ovrn bit is selected in control register 5. data can be retrieved when ovrn is set to ?1?, performing a 32 sample set reading from the output registers, data can be retrieved also on the wtm flag instead of ovrn if the application requires a lower number of samples. communication speed is not so important in fifo mode because data collection is stopped and there is no risk of overwriting acquired data. before restarting fifo mode, at the end of the reading procedure it is necessary to exit bypass mode.
first-in first-out (fifo) buffer AN4505 34/43 docid026441 rev 1 a fifo mode application hint is given below: 1. set fifo_en = 1: enable fifo 2. set fm[2:0] = (0,0,1): enable fifo mode 3. wait for the ovrn or wtm interrupt 4. read data from the gyroscope output registers 5. set fm[2:0] = (0,0,0): enable bypass mode 6. repeat from step 2 figure 17. fifo mode behavior if fifo mode is enabled, the buffer starts to collect data and fills all the 32 slots (from f0 to f31) at the selected output data rate. when the buffer is full, the ovrn bit goes high and data collection is permanently stopped; the user can decide to read fifo content at any time because it is maintained unchanged until bypass mode is selected. the read procedure is composed of a 32 sample set of 6 bytes for a total of 192 bytes and retrieves data starting from the oldest sample stored in fifo (f0). the ovrn bit is reset when the first sample set has been read. the bypass mode setting resets fifo and allows the user to enable fifo mode again. 6.3.3 stream mode in stream mode fifo continues filling, when the buffer is full, the fifo index restarts from the beginning and older data is replaced by the current. the oldest values continue to be overwritten until a read operation frees fifo slots. the host processor reading speed is most important in order to free slots faster than new data is made available. fm[2:0] bypass configuration is used to stop this mode. follow these steps for fifo mode configuration: 1. turn on fifo by setting the fifo_en bit to ?1? in control register 5 (0x24). after this operation the fifo buffer is enabled but isn?t collecting data, output registers are frozen to the last samples set loaded. 2. activate stream mode by setting the fm[2:0] field to ?011? in the fifo control register (0x2e). $0y w ),)2prgh hqdeoh ),)2 vwrs 2951 ),)20rgh hqdeoh ),)25hdglqj 6wduw),)2 5hdglqj ),)2 %\sdvv ? ? ? ? ? ) ) ) ) ? ) ? ? ) ) ) ) ) ) w vwrs 2951 ),)25hdglqj ? ? ? ? ? ) ) ? ) ? ? ) ) ) ) ) )
docid026441 rev 1 35/43 AN4505 first-in first-out (fifo) buffer 43 as described, for fifo mode, data can be retrieved when ovrn is set to?1? and by performing a 32 sample set read from the output registers, data can be retrieved also on the wtm flag if the application requires a smaller number of samples. figure 18. stream mode fast reading behavior in stream mode, the fifo buffer is continuously filling (from f0 to f31) at the selected output data rate. when the buffer is full the ovrn flag goes high and the recommended solution is to read all fifo samples (192 bytes) faster than 1*odr, in order to free fifo slots for the new angular rate samples. this allows avoiding loss of data and decreasing host processor interaction which increases system efficiency. if the read procedure is not fast enough, three different cases can be observed: 1. fifo sample set (6 bytes) is read faster than 1*odr: data are correctly retrieved because a free slot is made available before new data is generated. 2. fifo sample set (6 bytes) is read synchronous to 1*odr: data are correctly retrieved because a free slot is made available before new data is generated but fifo benefits are not exploited. this case is equivalent to reading data on the data-ready interrupt and does not reduce the host processor interaction compared to the standard accelerometer reading. 3. fifo sample set (6 bytes) is read slower than 1*odr: in this case some data is lost because data recovery is not fast enough to free slots for new angular rate data figure 19 . the number of correctly recovered samples is related to the difference between the current odr and the fifo sample set reading rate. $0y w 6wuhdp hqdeoh 2951 ),)25hdglqj 6wduw),)2 5hdglqj 6wduw),)2 5hdglqj ? ? ? ? ? ? ? ) ) ) ? ) ) ) ? ? ) ) ) ) ) ) w 2951 ),)25hdglqj ? ? ? ? ? ? ? ) ) ) ? ) ) ) ? ? ) ) ) ) ) )
first-in first-out (fifo) buffer AN4505 36/43 docid026441 rev 1 figure 19. stream mode slow reading behavior in figure 19 , due to slow reading, data from ?jj? are not retrieved because they are replaced by the new gyroscope samples generated by the system. figure 20. stream mode slow reading zoom after stream mode is enabled, fifo slots are filled at the end of each odr time frame. the read procedure must start as soon as the ovrn flag is set to ?1?, data are retrieved from fifo at the beginning of the read operation. when a read command is sent to the device, the content of the output registers is moved to the spi/i 2 c register and the current oldest fifo value is shifted into the output registers in order to allow the next read operation. in the case of a read slower than 1*odr, some data can be retrieved from fifo after that new sample is inserted into the addressed location. in figure 20 the fourth read command starts after the refresh of the f3 index and this generates a disconnect in the data read. the ovrn flag advises the user that this event has taken place. in this example, three correct samples have been read, the number of correctly recovered samples is dependent on the difference between the current odr and the fifo sample set read timeframe. $0y w 6wuhdp hqdeoh 2951 ),)25hdglqj 6wduw),)2 5hdglqj 6wduw),)2 5hdglqj ? \\ [[ ? nn o \\ mm o [[ ? ? ? )" )" ? ) ) ) )" )" ) ) ? ? ) ) ) ) 6dpsohv ryhuzulwwhq w 2951 ),)25hdglqj ? \\ [[ ? nn o \\ mm o [[ ? ? ? )" )" ? ) ) ) )" )" ) ) ? ? ) ) ) ) $0y 6wuhdp hqdeoh w 2951 5 ),)25hdglqj 6wduw),)2 5hdglqj 6dpsohv ryhuzulwwhq ? ? ? ? ? ) ) ) ) ) ) ? ) ) ) ) ) 5 5 5 5 w wgw wgw w 2951 5 ),)25hdglqj ? ? ? ? ? ) ) ) ) ) ) ? ) ) ) ) ) 5 5 5 5 w wgw wgw
docid026441 rev 1 37/43 AN4505 first-in first-out (fifo) buffer 43 6.3.4 stream-to-fifo mode this mode is a combination of the stream and fifo modes previously described. in stream- to-fifo mode, the fifo buffer starts operating in stream mode and switches to fifo mode when the selected interrupt occurs. follow these steps for stream-to-fifo mode configuration: 1. configure desired interrupt generator using register int1_cfg (0x30). 2. turn on fifo by setting the fifo_en bit to ?1? in control register 5 (0x24). after this operation the fifo buffer is enabled but isn?t collecting data, output registers are frozen to the last samples set loaded. 3. activate stream-to-fifo mode by setting the fm[2:0] field to ?011? in the fifo control register (0x2e). the interrupt trigger is related to the ia bit in the int1_src register and it is generated even if the interrupt signal is not driven to an interrupt pad. a mode switch is performed if both the ia and ovrn bits are set high. stream-to-fifo mode is sensitive to the trigger level and not to the trigger edge which means that if stream-to-fifo is in fifo mode and the interrupt condition disappears, the fifo buffer returns to stream mode because the ia bit becomes zero. it is recommended to latch the interrupt signal used as the fifo trigger in order to avoid losing interrupt events. if the selected interrupt is latched, the register int1_src must be read to clear the ia bit; after the read, the ia bit takes 2*odr to go low. in stream mode the fifo buffer continues filling, when the buffer is full, the ovrn bit is set high and the next samples overwrite the oldest. when the trigger occurs, two different cases can be observed: 1. if the fifo buffer is already full (ovrn = ?1?), it stops collecting data at the first sample after trigger. fifo content is composed of #30 samples collected before the trigger event, the sample that has generated the interrupt event and one sample after the trigger. 2. if fifo isn?t yet full (initial transient), it continues filling until it is full (ovrn = ?1?) and then, if the trigger is still present, it stops collecting data. figure 21. stream-to-fifo mode: interrupt not latched $0y 7uljjhu,$elw w 6wuhdpwr),)2 hqdeoh ),)2 vwrs 2951 ),)25hdglqj 6wduw),)2 5hdglqj 2'5 ? ? ) ) ) ,qwhuuxsworvw 7uljjhu,$elw w 2951 ),)25hdglqj 2'5 ? ? ) ) )
first-in first-out (fifo) buffer AN4505 38/43 docid026441 rev 1 figure 22. stream-to-fifo mode: interrupt latched stream-to-fifo can be used in order to analyze the history of the samples that generated an interrupt; the standard operation is to read fifo content when the fifo mode is triggered and the fifo buffer is full and stopped. 6.3.5 bypass-to-stream mode this mode is a combination of the bypass and stream modes described above. in bypass- to-stream mode, the fifo buffer starts operating in bypass mode and switches to stream mode when the selected interrupt occurs. follow these steps for bypass-to-stream mode configuration: 1. configure desired interrupt generator using register int1_cfg (0x30). 2. turn on fifo by setting the fifo_en bit to ?1? in control register 5 (0x24). after this operation the fifo buffer is enabled but isn?t collecting data, output registers are frozen to the last samples set loaded. 3. activate bypass-to-stream mode by setting the fm[2:0] field to ?100? in the fifo control register (0x2e). the interrupt trigger is related to the ia bit in the int1_src register and it is generated even if the interrupt signal is not driven to an interrupt pad. bypass-to-stream mode is sensitive to the trigger level and not to the trigger edge which means that if bypass-to-stream is in stream mode and the interrupt condition disappears, the fifo buffer returns to bypass mode because the ia bit becomes zero. it is recommended to latch the interrupt signal used as the stream trigger in order to avoid losing interrupt events. if the selected interrupt is latched, register int1_src must be read to clear the ia bit; after the read, the ia bit takes 2*odr to go low. in stream mode the fifo buffer continues filling. when the buffer is full, the ovrn bit is set high and the next samples overwrite the oldest. $0y 7u ljjhu,$elw w 6wuhdpwr),)2 hqdeoh ),)2 vwrs 2951 6wuhdpwr),)2 hqdeoh 5hdg ,1765& ),)25hdglqj 6wduw),)2 5hdglqj ),)2 %\sdvv ? ? ) ) ) ) ) ) ) ) ) ) 7u ljjhu,$elw w 2951 ),)25hdglqj ? ? ) ) ) ) ) ) ) ) ) )
docid026441 rev 1 39/43 AN4505 first-in first-out (fifo) buffer 43 figure 23. bypass-to-stream mode bypass-to-stream can be used in order to start the acquisition when the configured interrupt is generated. 6.4 watermark the watermark is a configurable flag that can be used to generate a specific interrupt in order to know when the fifo buffer contains at least the number of samples defined as the watermark level. the user can select the desired level in a range from 0 to 31 using the wtm[4:0] field in the fifo control register while the fifo source register fss[4:0] always contains the number of samples stored in fifo. if fss[4:0] is greater than wtm[4:0], the wtm bit is set high in the fifo source register, on the contrary, wtm is driven low when the fss[4:0] field becomes lower than wtm[4:0]. fss[4:0] increases by one step at the odr frequency and decreases by one step every time that a sample set reading is performed by the user. figure 24. watermark behavior - wtm[4:0] = 10 (hex) in figure 24 , the first row indicates the wtm[4:0] value, the second row indicates the relative fifo slot and last row shows the incremental fifo data. assuming wtm[4:0] = 10 (hex), the wtm flag changes from ?0? to ?1? when the eleventh fifo slot is filled (f10). figure 25 shows that the wtm flag goes low when the fifo content is less than wtm[4:0], which means that nine unread sample sets remain in fifo. the watermark flag (wtm) can be enabled to generate a dedicated interrupt on the drdy/int2 pin by setting the i2_wtm bit high in ctrl_reg3. $0y w %\sdvvwr6wuhdp hqdeoh 2951 ),)25hdglqj 6wduw),)2 5hdglqj 6wduw),)2 5hdglqj ) ) ) ) ) ) ? ? ) ) ) ? ) ) ) ? ) ) ) ? ? ? ? ,$elw 6wuhdp hqdeoh 6wuhdp glvdeoh $0y w ),)2 hqdeoh 2951 2951 ? ? ? ? ? ? ? ) ) ) ? ? ) ) ? ? ) ) ) ) ) ) :70 ),)25hdglqj 6wduw),)2 5hdglqj w 2951 2951 ? ? ? ? ? ? ? ) ) ) ? ? ) ) ? ? ) ) ) ) ) ) :70 ),)25hdglqj
first-in first-out (fifo) buffer AN4505 40/43 docid026441 rev 1 6.5 retrieving data from fifo when fifo is enabled and the mode is different than bypass, reading output registers (28h to 2dh) return the oldest fifo sample set. whenever the output registers are read, their content is moved to the spi/i 2 c output buffer. fifo slots are ideally shifted up one level in order to release room for a new sample reception and the output registers load the current oldest value stored in the fifo buffer. the whole fifo content is retrieved by performing thirty two read operations from the gyroscope output registers, every other read operation returns the same last value until a new sample set is available in the fifo buffer. data can be retrieved from fifo using every read byte combination in order to increase the application flexibility (ex: 196 single byte reads, 32 reads of 6 bytes, 1 multiple read of 196 bytes, etc.). it is recommended to read all fifo slots in a multiple byte read of 196 bytes (6 output registers by 32 slots) faster than 1*odr. in order to minimize communication between master and slave the read address is automatically updated by the device; it rolls back to 0x28 when register 0x2d is reached. in order to avoid losing data, the right odr must be selected according to the serial communication rate available. in the case of standard i 2 c mode being used (max rate 100 khz), a single sample set reading takes 830 s while total fifo download is about 17.57 ms. i 2 c speed is lower than spi and it needs about 29 clock pulses to start communication (start, slave address, device address+write, restart, device address+read) plus an additional 9 clock pulses for every byte to read. if this recommendation were followed, the complete fifo read would be performed faster than 1*odr which means that using a standard i 2 c, the selectable odr must be lower than 57 hz. if a fast i 2 c mode is used (max rate 400 khz), the selectable odr must be lower than 228 hz. figure 25. fifo reading diagram - wtm[4:0] = 10 (hex) in figure 25 ?rx? indicates a 6-byte read operation and ?f0*? represents a single odr slot stretched for the diagram. $0y w ),)2 hqdeoh 2951 ? 2951 ? ? ? ? ? ? ) ) ) ) ? ) ? ) :70 5 ),)25hdglqj 6wduw),)2 5hdglqj 5 ? ? 5 ? ? 5 5 5 ? ? ? (037< ),)2(psw\ (037< ? ? 2951 ? ? ? ? ? ? ) ) ) ) ? ) ? ) 5 5 ? ? 5 ? ? 5 5 5 ? ? ? (037< ?
docid026441 rev 1 41/43 AN4505 temperature sensor 43 7 temperature sensor the l3gd20 is provided with an internal temperature sensor that is suitable for delta temperature measurement: only sensitivity is calibrated while offset is not calibrated . temperature data are generated with a frequency of 1 hz and are stored inside the out_temp register in two?s complement format with a sensitivity of -1 lsb/c. 7.1 example of delta temperature data calculation in table 34 we show an example of the content of out_temp. we select the content of the out_temp register in two different moments, t1 and t2 and we calculate the temperature delta between moment t1 and moment t2. we can calculate temperature shift as: deltat = out_temp@t2 ? out_temp@t1 = -5 lsb. using the sensitivity information we get: deltat = -5 lsb * -1c/lsb = +5 c. table 34. out_temp register content out_temp time binary hex 00000100 4 00000011 3 00000010 2 t1 00000001 1 00000000 0 00001111 -1 00001110 -2 00001101 -3 t2 00001100 -4
revision history AN4505 42/43 docid026441 rev 1 8 revision history table 35. document revision history date revision changes 18-jun-2014 1 initial release.
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